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Tuesday, 4 June 2013

Job Requirement For SOC/IP DFT Engineer - India-JOBDRAG

Job Requirement For SOC/IP DFT Engineer - India
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Job Summary
Job Code:JB46587
Posted on:2013-06-03
Expiry Date:2014-06-03
Functional Area:IT-Hardware|Networking
Job Role:DFT ENgineer
Location:BANGLORE ,
Job Specification
Gender:Both
Nationality:Indian
Job Type:Permanent
Experience:1 - 4  Years
Qualification:B.E/B.Tech - Others
Offered Salary:Upto: 0 INR Anually
Job Details
Job Description:
  • Good Basic understanding of all concepts of DFT including scan, ATPG, Memory Testing, I/O testing, Analog testing etc.
  • Should have hands on experience of SCAN, ATPG (stuck-at and TFT mininum)
  • Well versed with test protocols like JTAG and/or IEEE1500
  • Should have used industry standard DFT tools from either Mentor, Synopsys or Cadence.
  • Good DFT verification skills covering RTL and GLS simulation debug would be a plus point.
  • Theoretical/practical knowledge of advanced fault models and low power DFT concepts would be a plus point
Desired Profile:Should have used industry standard DFT tools from either Mentor, Synopsys or Cadence.Good DFT verification skills covering RTL and GLS simulation debug would be a plus point.Theoretical/practical knowledge of advanced fault models and low power DFT concepts would be a plus point
Key Skills:Should have used industry standard DFT tools from either Mentor, Synopsys or Cadence. Good DFT verification skills covering RTL and GLS simulation debug would be a plus point. Theoretical/practical knowledge of advanced fault models and low power DFT concepts would be a plus point
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