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| Job Description | : | Should be familiar with EDA tools: Cadence Virtuoso, Encounter, Mentor Calibre, Synopsys circuit simulation & static timing tools. Set up design project environments including project structure, revision control, Cadence Virtuoso environment (Schematic capture, layout design, and simulation environment), Standard Cell Library, DRC, LVS, parasitic extraction flows, Synthesis, auto place and route, static and dynamic timing verification flows in a mixed-signal design project.(comprehensive front to back). |
| Desired Profile | : | Job Description:Provide technical and personnel leadership to a team of engineers involved in developing and deploying state of the art mixed-signal design flows, EDA tool support and methodology development. Work with highly motivated team that focuses on high quality, timely delivery of efficient design environments. Should be able to work effectively in an organization spread across multiple geographic locations. Candidate should have exposure to current sub-micron CMOS process technology (e.g. 22nm & 28nm), mixed-signal design flow and design methodology challenges. Requirements:• B.S. or M.S. in Electrical Engineering or Computer Science with at least 10 years of experience in flow development and CAD tool support for mixed-signal IC Design projects.• Minimum 3 years of experience managing a team of engineers. • Should have led at least five or more designs through tape-out. • Should posses expertise in a broad area – digital design flows, custom design flows, inteal and exteal customer support, license and LSF management and EDA tool vendor management• Hands-on experience in Cadence Virtuoso p-cell development, foundry PDK installation, debug and support• Hands-on experience in RTL-GDSII flow for digital design. • Should be familiar with EDA tools: Cadence Virtuoso, Encounter, Mentor Calibre, Synopsys circuit simulation & static timing tools. Set up design project environments including project structure, revision control, Cadence Virtuoso environment (Schematic capture, layout design, and simulation environment), Standard Cell Library, DRC, LVS, parasitic extraction flows, Synthesis, auto place and route, static and dynamic timing verification flows in a mixed-signal design project.(comprehensive front to back).• Good presentation, communication, organizational and leadership skills and qualities is a must. |
| Key Skills | : | Cadence Virtuoso p-cell development, foundry PDK installation, debug and support, RTL-GDSII flow , EDA tools: Cadence Virtuoso, Encounter, Mentor Calibre, Synopsys circuit simulation & static timing tools |
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